It has nothing to do with the size of any wires. The chip itself is a solid wafer of silicon with a tiny bit of copper, aluminum, etc deposited on top. It's all one solid piece though, the silicon die itself is never going to be damaged from shock unless it's strong enough to break it in half which isn't going to happen before the rest of the device is toast.
There's tiny bond wires that connect the silicon die to the pins on the outside of the chip but that has nothing to do with the process size of the chip. Basically the feature size just means that somewhere on the die there's a tiny spot 7 nm wide. It's a measure of how fine they can get it when etching and doping a silicon wafer.
"Basically the feature size just means that somewhere on the die there's a tiny spot 7 nm wide."
Understood. And these tiny spots are not brittle you say. Presumably because of embedding?
It's sort of like measuring the wood grain of a log. The wafer is solid but the wells are measurable, just like the log is solid but the grain can be measured.
There's tiny bond wires that connect the silicon die to the pins on the outside of the chip but that has nothing to do with the process size of the chip. Basically the feature size just means that somewhere on the die there's a tiny spot 7 nm wide. It's a measure of how fine they can get it when etching and doping a silicon wafer.