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On-Chip Interconnection Architecture of the Tile Processor (2007) [pdf] (princeton.edu)
31 points by steven741 8 months ago | hide | past | web | favorite | 13 comments



Ahh Tilera. When MIT's RAW architecture went commercial and became Tilera, it looked like the multicore future was finally coming. They had a lot of nice devtools, like an eclipse-based simulator that let you visualize what was going on in the chip. 64 cores was really appealing, but because they didn't have floating point in the first set of chips, people mainly used them for network processing. Then.. Intel started talking about Larrabee (why use Tilera when you could just run p54c x86), and Nvidia started to become more programmable via Cuda.

Eventually EZChip acquired Tilera (2014), which was then acquired by Mellanox (the hpc network company). Last I saw (2016), Mellanox was using trying to put the tilera stuff in the BlueField products (NVMe over Fabrics target, I think):

https://www.hpcwire.com/2016/06/01/mellanox-spins-ezchip-acq...

Anyone know what happened with BlueField?


BlueField is currently shipping in "smart NICs" and should be shipping as the host processor in storage appliances by the end of the year. It seems to be the cheapest and lowest-power option at the moment for getting PCIe gen 4 IO, compared to IBM's POWER9. They definitely abandoned the approach of having a very large number of weak cores after being acquired, but they're still using a mesh interconnect based on the Tilera IP.


I once found a development motherboard for the RAW processor at a MIT loading dock ( https://flic.kr/p/Fw8cKb ). I always wondered what happened to the project. Thanks for the full history!


Hmmm, I think my new how-can-I-figure-out-how-to-do-that might be coming up with creative ways to be a recycling center's loading dock coordinator. More specifically, it sounds like I want to be the person in charge of disposals.

Now to figure out how to make this happen....


You seem to know a lot. Any nice startups in this space?


Greenarrays is still going. They've made some new app notes.

I've found the 64x18b word limitation of memory per computer much less daunting than I did at the beginning, simply because how amazingly terse you can make your code. You also end up just simplifying, making your look-up-table or other array 8 or 16 words long...sometimes 32 or 64, but that's a bit more work.

One experiment I've done with it is harnessing 95 simultaneous cores for a virus vat, with a 47 core vat enclosure keeping it from hanging. The last 2 nodes are I/O and the probe to see what's going on. The virus is exactly one 18b word.


How about SiFive


In general purpose parallel processors? Ambric had some interesting tech


This looks really similar to that adapteva chip a few years back..

http://adapteva.com/docs/epiphany_arch_ref.pdf


Are those things even for sale anymore? Did a (quick) google search and found one on e-bay and that's about it.


Tilera evolved into Mellanox BlueField, although it's not clear whether the tile interconnect is still used. https://www.hpcwire.com/2016/06/01/mellanox-spins-ezchip-acq...


Sort of. Tilera got acquired EZchip Semiconductor who merged with Mellanox Technologies. However, support for the TILE architecture isn't what it used to be.

http://www.mellanox.com/page/multi_core_overview?mtag=multi_...


The tile architecture was dropped from the Linux kernel in 4.17

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/lin...




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