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That was a bit misleading in some ways. First, in pipelining you'll typically measure how long a pipeline steps in FO4s, which is to say the delay required for one transistor to drive 4 other transistors of the same width. Intel will typically design its pipeline stages to have 16 FO4s of delay. IBM is more aggressive and will try to work it down to 10. But of those 10, 2 are there for the latches you added to create the stage and 2 are there to account for the fact that a clock edge doesn't arrive everywhere at exactly the same time. So if you take one of those 16 FO4 Intel stages and cut it in half you won't have a two 8 FO4 stages but two 10 FO4 stages. And since those latch transistors take up space and energy you're got some severe diminishing returns problems.

One thing that's changed as transistors have gotten smaller is that leakage has gotten to be more of a problem. You used to just worry about active switching power but now you have to balance using higher voltage and lower thresholds to switch your transistors quickly with the leakage power that that will generate.

And finally velocity saturation is more of a problem on shorter channels making current go up more linearly with the gate voltage than quadratically.




Good points. One thing I would like to emphasize is the issue with clocks not arriving everywhere at the same time. Balancing the clock tree over a chip gets harder and harder.

But the clock setup, hold times also gets shorter and shorter when the clock frequency goes up. The clock signal will have jitter. The end result is that less and less time of the clock edge is usable to sample the signal into the register.

And this in turn put a strain on how well balanced the logic between the registers are. To allow all signals traverse the logic paths through the gates and stabilize in time to be sampled.

To add to the complexity, as we move down the geometries, the difference in performance of different transistors becomes relatively larger. One rason for this is that oxide layers consist of (in average) fewer and fewer molecules. When the layer was made up of 100 molecules, 101 or 102 didn't really make much of a difference. But when the average is 4 molecule one more or less will have a huge impact on the performance.

So controlling variance (clock tree balance, jitter in clock generatiom, imbalances between paths and variance in chip production) becomes ever more problematic and important.


How do you know all this stuff?


Got my master's in it, before ending up in sensors then robotics instead. And a continued interest, I guess.

Here are some free relevant courses. You might have to go back and take the pre-reqs.

https://ocw.mit.edu/courses/electrical-engineering-and-compu...

https://ocw.mit.edu/courses/electrical-engineering-and-compu...


How does one get into robotics? I have not looked much but none of my local schools seem to have "robotics".

I tinker with electronics and make some remote controlled robots for fun (internet controlled, live video with multi user input, sort of crowd controlled). I am now trying to self teach myself about kalman filters and control theory and want to build more autonomous robots.

But any info on getting into robotics for a day job would be nice.


Well, my path was finding doing the motion control on giant dish radars really satisfying then do well in an interview because you know can speak fluently about Kalman filters. But really you should be able to be useful on a robotics team if you have good programming, electronics, or mechanical engineering skills and then learn more on the job. Learn one of those deeply and ideally a few things about the other two as well.


There are other ways to get into any field besides studying it in school, but if you are going to go to school anyway and want to study something directly relevant to robotics, how about a mechatronics or a controls engineering program?


Thank you for this! I have been looking for IC design MOOCs for awhile.


In case you're wondering, FO = Fan Out.


I don't think anyone uses U/LVT transistors in low geometries, the leakage would be a nightmare .


I know a lot of people using LVT transistors in 28 and 16/14nm processes, including relatively low power (mobile and embedded) designs. I personally have used LVT variant SRAM blocks for both our 28nm and 16nm designs, and ULVT cells manually placed for critical path for Neo's FPU for our 28nm chip.


I should've rephrased: I don't know of anyone* who uses ULVTs exclusively, to answer the parent of using ULVTs to increase speed.

* Okay, I know of some people, but their design is different.


I'm not surprised, though I don't have a good sense of what the exact numbers are.


Leakage diff @ 125 degrees celsius is about one order of magnitude.


Anywhere where I can read more on this?




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