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The TL;DR; of this article is:

"...a simple ASIC (say one that is a few square millimeters in size, fabricated using the 250-nm technology node) might cost a few thousand bucks for a couple dozen samples."




There's a lot of people quoting the price in this thread but very few coming forwards to say "yes, I've actually done this".


Everyone who took a grad class in VLSI layout has done this, it really isn't uncommon.


The number of people with the experience, knowledge, cash, and who are not bound by NDA is very small.


I studied Electronic Systems Engineering, and particularly enjoyed my classes in circuit design, including writing a basic CPU in Verilog and deploying it to an FPGA.

My summer jobs in university were for software companies, because it's easier for software devs to make something useful in a couple of months, and I was more interested in the company's location than the type of work.

I think I want to get back into hardware. I just transferred with my boss from a spin-off to a parent company, and the large company has absurd policies that bother me. Everything done during working hours belongs to the company, so all my side projects are on hold. They don't keep me busy with company projects though, so I'm really bored a lot of the time (and end up here on Hacker News). The side projects (e.g. Chinese learning) are totally unrelated to the company's business (control systems for microSD testing equipment), but it's futile to oppose the policy.

What's it like on the hardware side? If I get a job doing hardware, but have idle time in the office, am I allowed to pursue my own side projects and publish those on Github? That would encourage me to make the leap.


Literally everyone who has done this is bound by NDA. Every single foundry will make you sign one.


Having signed the a couple of those NDAs. The foundries are mainly concerned about their standard cell library, and any information that may let a competitor understand the details of their lithographic process. Most engineers just use the cell library from foundry, but cell library does contain information about a foundry's process.

A lot foundries will let you make chips without using their cell library. You some times have to make complete custom components in the analog world. (Be warned this a ton of work and is no easy under taking)

However, even if you developed your own cell library for a particular foundry. It will still be tied by an NDA since it may leak information about how the foundry handles optical proximity correction and uses phase shifting (of light) for their process to increase resolution. Also how many layers it takes to implement something and how each of those layers have particular characteristics may reveal some of the chemistry and material science used to dope the silicon or create certain structure for their process.

~edit a few typos/omissions~


How much of this was "simulatable" -- either by Cadence or Magic?

What's the average number of tries to get something right?

How'd you end up in this business?


So cadence for instance lets you create device models. For instance if we are making a simple inverter some things you would need are: width and height, channel (width x height), Zero bias voltage, Zero-bias depletion capacitance (Planar and Sidewall), Channel length, Surface potential, Oxide Thickness, Carrier Saturation speed, Junction Grading, Area diffusion, Transconductance, Carrier Mobility,

The list goes on. So once you get this information you can create a model file that will let simulate your simple NOT gate. However, if you are starting from scratch such as there is something that does not exist in the standard cell library. You can't just measure these properties since the device does not exist yet. So you have run other simulation software to get reasonable values as calculating them by hand is not pretty. Also to get these values you may need information from the foundry. For instance Intel's finfet transistor behave differently in some regards compared to a traditional planar transistor (mainly the channel). Intel is not going to just tell you how they work so you can get accurate model of them without an NDA. Also a foundries process can effect your design as layer thickness can changes such capacitance. So the big thing is cadence does not let you model

Cadence also can only simulate a limited number of devices. So for large designs/system you can't simulate the whole thing. So you can only simulate sub components for big designs. It's also slow to simulate large design again pushing you to smaller simpler sub components. It's limited to things you can generate a net list for. It additionally will let calculate cross voltages. I could keep going on and on, but there is only so much I can cram into a hacker news response.

Depends on who you are working for and what you are making. However, you generally use 2 spins for a large device. I bet you have heard the term engineering silicon. That's usually the first spin. If there are problems usually the only changes are made to metal (wiring) layers of the masks. If a serious problem is discovered it may require a complete re-spin. That's if you mainly using the standard cell library provided by the foundry. If you are making something from scratch that's whole other story. However, you still generally build into your design other elements that let you shut off defective parts or include redundant elements to increase the chance of one elements working. So the designs also include a lot additional circuits and logic that you may not be aware of for debugging and testing purposes. If you can't get the device perfect you still may sell use it and publish an errata or more specify a more limited range of operation.

I'll just say I am computer engineer. My first job was at Micron.


Yes, God forbid you need native (low threshold) devices... want to minimize NWell spacing for stacked devices while preventing ESD latch-up... care about capacitance density or voltage variation.

Basically, if you are designing mixed-signal/analog then your PDK (Process Development Kit) either comes from a tier1 foundry (TSMC/UMC), the process is a very good copy (SMIC/GF), or you need a year of support and a one or more full time process support engineers.




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