I've never understood why people don't get more excited about memristors. They could replace basically everything. Assuming someone can master their manufacture, they should be more successful than transistors. Of course, I'm still waiting to be able to buy a 2000 ppi display like IBM's R&D announced creating back in the late 1990s or so... so I guess I'd best not hold my breath.
personally, mostly because i've been seeing articles about how they're just about to totally upend computing for the last ten years
I know that sounds like tautological nonsense, but the trick comes down to predicting when these things will become real rather than if they become real. From my experience, if you want a good indication, look at price/performance trends for a particular technology. If that technology has no price/performance data, look at the price/performance data of its components or related technologies.
If you can't find price/performance data, then don't get too excited yet.
The funny thing is that if you reread Wired's article about Push, which they've been made fun of for ever since writing it, the only thing that hasn't come true is the technologies they predicted would power it. But other than that it's a perfect description of Reddit, Facebook, YouTube, etc.
You can find references and hints to them all the way back to maxwell's day. They tended to be regarded as anomalous circuits back then however.
They've been theorized since 1971 mathmatically but until fairly recently haven't been a thing.
It is the fourth fundamental circuit, give it a while before discounting it. And be happy you're alive when the fourth fundamental circuit was discovered and made real.
.... this lecture: http://cse.unl.edu/~seth/434/Web%20Links%20and%20Docs/Feynma...
I skimmed the paper and enjoyed the illustrations, and the photos at the end :).
So Memristors are about reversible gates instead of non-reversible NAND gates?
So I think it's more that memristors would be a solution that allows the use of reversible gates making for more reliable processors. If anybody else has any better insight, fire away.
>. Another plan is to distribute very large
numbers of very simple central processors all over the memory. Each one deals with
just a small part of the memory and there is an elaborate system of interconnections
between them. An example of such a machine is the Connection Machine made at
M.I.T. It has 64,000 processors and a system of routing in which every 16 can talk
to any other 16 and thus 4000 routing connection possibilities.
Those are the two things you need to look for. No proof of concept? Well, talk is cheap! Have a proof of concept, but the advantages aren't clear? Again, talk is cheap. Refine it until the advantages are demonstrable!
So the bleeding edge is where I want to be.
I was convinced this meant they knew memristors were going to kill hard drives soon and they were profit taking before killing them off.
That’s been more than ten years now. I am still waiting, but made other plans.
For the same reason they aren't excited about flying cars?
Because they wait until something is actually delivered that in a form they can use?
You're not thinking of this and mistakenly adding an extra 0, are you? https://en.wikipedia.org/wiki/IBM_T220/T221_LCD_monitors#His...
Who was right about what?
> They are the equivalent of second generation laser printers.
What does this even mean?
But now you've got smart phones pushing in the region of 400 PPI. It's smoother, and make Apple displays look like laggards. But they're beyond the point where most eyes notice the difference without magnification.
The Apple Watch and most iPhones (including the original Retina display on the iPhone 4) are around 300-400 PPI, with the X being 458. Only Apple's "Retina" laptop/iMac displays have been around 220, which normally looks great given the increase in the viewing distance.
Wikipedia has a pretty nice breakdown of the PPI of all Retina displays Apple has shipped:
I think Apple displays look completely fine (much better than average, in fact, since they focus so much on color accuracy).
The ridiculous Android PPI arms race is one reason why iPhones are way ahead in all performance benchmarks. What's the point of all those extra pixels you can't even see if the GPU can barely manage to fill them?
I do joke though that some day Apple will introduce iGlasses, which will be AR glasses with electronically adjustable refractive indexes. When it detects a smartphone in front of your field of view it will zoom in 2x and do image stabilization so you can see your 500 ppi screen.
Like a high tech version of the computers in Brazil...
HP’s first 2G laser (LaserJet w/ Canon CX engine) was 300 dpi in 1984.
Also I had a 600 dpi LJ 4 which was released in 1992.
There might be clever ways to make a particular circuit dual purpose or something (Storage element that can do math on itself? A math pipeline that doesn't need pipeline flops?)
But arbitrary reprogrammability is already here. It's called an FPGA, and it sees only niche use, not in the least because developing a bitstream to program it with is a huge chunk of work. So the days of a chip that constantly morphs like a chameleon to unrecognizable new forms is probably a long way in the future.
I like to remind myself the industry is called VLSI- very large scale integration. In other words, the job is not about transistors. More than anything else, it's about managing the complexity of billions of transistors. Digital CMOS is a great example; transistors can already do so much more than CMOS, but it's a massively simplifying design scheme.
Of course, the reason we don't see that is the economics aren't great, the performance boost isn't either, and developing those utility bitstreams is a herculean task by itself.
The real world incarnation of all this I would argue is the SoC. Silicon is cheap enough you don't make one mighty morphic chip; you make several dedicated IP's and put them all on one chip.
You're wrong, this is called partial reconfiguration.
An FPGA isn't really a "gate array," but a huge ensemble of small lookup tables that are made with what amounts to very fast static RAM. If major FPGA manufacturers didn't guard their bitfile formats with their lives, it's possible that entirely new fields of research would have emerged to find new ways to take advantage of the existing hardware in these chips, much like what GPGPU researchers have done with graphics cards.
I wonder how expensive it would be to make a really really tiny FPGA with a few tens of cells in it.
As in, I realize chip design is expensive and crazy complicated, but small runs are only around $5k or so. I'm wondering if FPGAs manufacturing has similar costs - or at least similar-ish enough to be potentially interesting.
If you could go from zero to tiny prototype FPGA with 5 or 6 figures, you might just be able to pull some VC money out of thin air to kickstart with. Or you might not even need to go in the VC direction, there's bound to be a group of people out there with collectively enough between them to kickstart something like this. I'm uncertain if Kickstarter would be a horrible disaster.
With prototypes made, you'd just need to send a few of the prototypes out to some smart PhDs and hardware hackers, get them to show what's possible, and that could be a viable way to get further investment and complete the bootstrap cycle.
Obviously the point of all of this is to make a chip that's as open as reasonably possible. Physical chip manufacturing is likely to be NDA'd (for example the SRAM would probably be supplied as a reference design from the foundry) but the "how to poke this with software" could be super open. Would be fun.
Why do they?
Especially at the high end, the manufacturers commonly introduce new hardware constructs -- high-speed transceivers, clock generators, memory controllers, that kind of thing -- and they don't really want to document and disclose the inner workings of these components at a level that would allow third parties to write tools for them. It could potentially take a non-trivial amount of documentation and customer support work. Meanwhile they want to preserve their trade secrets, and they also don't want to attract infringement suits from either patent trolls or legitimate competitors. Disclosure of bitfile formats would open those particular kimonos a bit too wide for comfort. This is largely why Linux users can only get GPU support via binary blobs.
At the low end, some good reverse-engineering progress has been made by people like Clifford Wolf on the Lattice parts. This work is certainly important, but as long as there's reasonably rapid technological progress on the hardware side, reverse engineering is never going to be enough to sustain a healthy third-party tools industry.
It's a real shame. Imagine how far we'd (not) have come if Intel and Motorola had walled off their instruction sets...
"The researchers believe this new prototype technology will enable ultra-dense, low-power, and massively parallel computing systems that are especially useful for AI applications."
So it seems that would benefit AI/Machine Learning more than GP processing, from that statement.
Fun to think about: in this scenario, the main job of an "optimizing compiler" would be to organize things spatially so that, as a calculation moved around in memory, it always found itself right next to the data it needed, when it needed it.
Besides, computational memory is not restricted to SIMD. It's limited into local memory, but not at synchronized execution.
I'm not holding my breath for more than 1% of programs to use this. Or if it gets built into GPUs, then 1% when possibly excluding rendering code.
My excitement is tempered by considering the areal demands on the silicon for the putative "smart memory". Suppose, just for the sake of argument, you want your smart memory to be able to take a 4K block of 64-bit integers and add them together. It happens incredible quickly, sure, though you'd have to get an expert to tell me what the fanin can be to guess how many cycles this will take. But you're now looking at massively more silicon to arrange all that. And adding blocks of numbers isn't really that interesting, we really want to speed up matrix math. Assuming hard-coded matrix sizes, that's a whackload of silicon per operation you want to support; it's at least another logarithmic whackload factor to support a selection of matrix sizes and yet more again to support arbitrary sizes. In general, it's a whackload of silicon for anything you'd want to do, and the more flexible you make your "active memory" the more whackloads of silicon you're putting in there.
It may sound weird to describe a single addition set of gates as a "whackload", but remember you need to lay at least one down for each thing you want to support. If you want to be able to do these operations from arbitrary locations in RAM, it means every single RAM cell is going to need its own gates that implement every single "smart" feature you want to offer. Even just control silicon for the neural nets is going to add up. (It may not be doing digital stuff and it may be easier to mentally overlook, but it's certainly going to be some sort of silicon-per-cell.)
Even if you were somehow handed a tech stack that worked this way already, you'd find yourself pressured to head back to the architecture we already have, because the first thing you'd want to do is take all that custom silicon and isolate it to a single computation unit on the chip that the rest of the chip feeds, because then you've got a lot more space for RAM, and you can implement a lot more functionality without paying per memory cell. And with that, you come perilously close to what is already a GPU today. All that silicon dedicated to the tasks you aren't doing right now is silicon you're going to want to be memory instead, and anyone making the smart memory is going to have a hard time competing with people who offer an order of magnitude or three more RAM for the same price and tell you to just throw more CPUs/GPUs at the problem.
RAM that persists without power is much more interesting than smart memory.
1. They're really hard to program for in a way that is easy to understand and scale.
2. They eat a ton of power. Heat = power = max speed. If you can't make it better then today existing ASICs are still going to be used.
The intersection of ASIC + reconfigurable serial processes(aka sequential programming) strikes a really sweet point between power and flexibility that I think is going to be hard to unseat.
I think FPGAs are incredible but if this were true I think we'd already see them taking over the world.
so you don't see the potential combination of this and that?
And that's BEFORE you do any of the exotic research of moving the computing elements around during operation. Just imagine if there was no memory hierarchy, where accessing a byte in mass storage is as fast and as easy as accessing a register. Quantum computers can't replace commodity hardware and there's no reason to think they will. Memristors, on the other hand, are one of the fundamental circuit elements and are destined to become as widespread as resistors, capacitors, and transistors.
(ok that was a long way to make a Schrödinger joke) There are a lot of people who are very excited about Quantum computers and working on them, as they get more 'real' people on the fence move over, etc. I watched this on a smaller scale with 3D printers, as only a few people were excited about them and then as they demonstrated more and more interesting things the wave of excited people expanded outward from that core.
But yeah, their mostly non-existance is exactly why people aren't more existed.
Probably because they have been promising them too long. I remember watching a video lecture in 2008 about how IBM was on the verge of revolutionizing everything with them.
Meanwhile in the same timespan GPU/DNN have upended the computing landscape.
Is this article about memristors? That wasn't clear. Can memristors perform computations?
Specifically as current is run across it, it builds up more and more resistance. Then as the current is reversed (the plus and minus ends of the resistor is switched) this resistance will go back down.
Thus it can be used as non-volatile memory in the sense that certain tiers of resistance can be designated as a bit.
Note that as it is fundamentally an analog component one can potentially also used this property to emulate a neuron.
That's incredibly interesting, especially the idea that it could be used to emulate neurons. I expect that it'd be hard to fabricate them with a very high branching factor, but as I've amply demonstrated, I know very little about this topic.
For anyone who is interested in a simple model of how the brain does this, check out "associative memories". The basic idea is that networks of neurons both store memory (in their synapses) and perform the computations to retrieve or recall those memories.
A simple example is the Hopfield network, a single layer of neurons that are recurrently connected with a specific update function: https://en.wikipedia.org/wiki/Hopfield_network
Another is two layers of neurons that are reciprocally connected called a Bidirectional Associative Memory (BAM): https://en.wikipedia.org/wiki/Bidirectional_associative_memo...
UPDATE: Looks like memristors production didn't work out for them: https://www.extremetech.com/extreme/207897-hp-kills-the-mach...
I found this article very useful in understanding what the work was about..
They are using phase change memory to store data and perform computations.
edit So HP built one with 160Tb of memory, I remember it being proposed with memristors but haven't been able to check if the prototype used them... Does anyone know what is different about IBM's that let's them claim this as a first though?
Caxton Foster's book is the major text I know on the subject.
Depends what you mean by "architecture". I disagree that a network of computers is comparable to colocating a computing unit with its memory. There are orders of magnitude in difference in communication costs and failure modes, so at some point you just have to acknowledge that the models are fundamentally different, and should be treated as such.
Certainly they are Turing equivalent, so they aren't more "powerful" in a computability sense, we but what's more interesting is the tradeoffs in computational complexity.
>scientists have developed the first “in-memory computing”
as your normal GPUs have register and cache memory mixed with the processors. I think the novel feature is they are mixing the processors with non volatile flash like memory rather than with RAM. Which I guess is interesting but the "will speed up computers by 200 times" presumable refers to an old school architecture rather than something like the 15/125 TFLOP Volta GPU which I'd imagine is faster than their thing. (https://news.ycombinator.com/item?id=14309756).
Unfortunately for neuromorphics, just about everyone else in the semiconductor
industry—including big players like Intel and Nvidia—also wants in on the
deep-learning market. And that market might turn out to be one of the rare cases
in which the incumbents, rather than the innovators, have the strategic
advantage. That’s because deep learning, arguably the most advanced software on
the planet, generally runs on extremely simple hardware.
Karl Freund, an analyst with Moor Insights & Strategy who specializes in deep
learning, said the key bit of computation involved in running a deep-learning
system—known as matrix multiplication—can easily be handled with 16-bit and even
8-bit CPU components, as opposed to the 32- and 64-bit circuits of an advanced
desktop processor. In fact, most deep-learning systems use traditional silicon,
especially the graphics coprocessors found in the video cards best known for
powering video games. Graphics coprocessors can have thousands of cores, all
working in tandem, and the more cores there are, the more efficient the
But that said, I'm excited that 90s technology is finally being adopted by the AI world. I'm also hopeful that all these languages like Elixir, Go and MATLAB/Octave will let us do concurrent programming in ways that are less painful than say OpenCL/CUDA.
Even a subset of the idea, having blit in ram (swap, row/col-zeroing, etc etc) could reduce pressure on the memory bus.
Delivering Software for Memory Driven Computing
Disclaimer: Neuromorphic computing with PCRAM devices is my MSc and future PhD thesis topic.