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Watching Ben's videos inspired me to finally assemble my Brainfuck-based CPU. That is to say, its native instruction set is Brainfuck.

https://hackaday.io/project/4237-mental-1-a-brainfuck-cpu/lo...

And a more recent video, showcasing PS/2 keyboard input: https://twitter.com/treykeown/status/867809790294097920




Sometimes I forget how crazy hackers are, and then someone goes and builds a CPU... and uses BF as an instructions set. Thank you :)


It's impractical, but it's not theoretically out-there: Brainfuck is essentially a minimal Turing-machine system. Someone attempting to build a computer based soley on Turing's "On Computable Numbers" might very well wind up with something like a Brainfuck-CPU.


Exactly, the beauty of the internet is that its taught us that we are not alone. We are legion.


I've been doing the same thing for the past couple weeks. http://blog.cogwheel.info/2017/05/ttl-brainfuck-computer-par...


Slick work! I've been on the hunt for similar projects to compare approaches, but I haven't find many implementations outside of FPGAs.

I like the approach for handling [ and ]. My design is "dumb" in the sense that it uses a `scan` register to handle jumping forward and backwards (so it's quite slow). So far it seems easiest to bite the bullet and scan forwards when [ is zero, but have something similar to your stack pointer for jumping back. Building the jump table for both [ and ] on reset is also a nice optimization.


Thanks :) I love that I'm not the first/only one to do one of these in Brainfuck (especially in direct response to Ben's series).

I have a feeling the approach I take will follow from whatever I decide for RAM zeroing. The purist in me is still a bit put off by the idea of preprocessing. It feels more like a compiler+CPU rather than just a CPU. If I go the "highest address counter" approach where I synthesize zeros the first time a RAM location is passed, I probably won't do the loop pre-processing.

I could do a hybrid approach where both jump points are indexed the first time the loop is scanned. This would achieve amortized constant time. I think I could live with that...


That's amazing! And there was me half-thinking about writing an interpreter as an exercise...

Edit: Have you posted this as a 'show hn'?


Not yet! I have a bit of work to do before trying to show this project. There's a MENTAL-2 being built right now, and a few software tools I need to clean up. Hoping to get it up to at least 1MHz.




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