There are thousands of people invested in the next CNN, GPU, CPU, TPU, or FPGA architecture. Having a few smart people with demonstrated experience try an idea that doesn't fit the current biases in the field is perfectly reasonable funding allocation and great for science. If there weren't neural net holdouts getting funding doing something that didn't seem like it would work we'd be still using SVMs or arguing about probablistic graphical models.
If you think this approach isn't warranted, I suggest that your example of an LSTM chip is also not sensible. First why not something simpler like GRU, secondly it's not compute efficient for the memory stored as compute scales poorly due to the matrix multiply for the size of your hidden state vector. If in a couple months we have a new differentiable memory architecture (a la neural Turing machine) all the work you did building a chip is outdated!
Starting with first principles of what you can efficiently do with current process technology combined with an understanding of computational neuroscience is what Kwabenas lab excels at.
It's actually very difficult to simulate the mixed analog digital asynchronous chips coming out of Kwabenas lab or elsewhere in the industry.
There are plenty of other academic chips that fail after tapeout. Kwabenas lab has a proven track record of taping out chips that does what he claims. So from a hardware perspective I'd rather bet on a guy who has successfully taped out dozens of chips in his lab, and have the rest stick to simulation.
The comment above yours reminds me of all the times deep learning had been dismissed in the past as useless until computers finally were fast enough to make it actually usable. Now they are heralded as the best thing in the world.
People always dismiss everything which doesn't fit the current favorite of the month. Short term thinking, the bane of the world.
If you think this approach isn't warranted, I suggest that your example of an LSTM chip is also not sensible. First why not something simpler like GRU, secondly it's not compute efficient for the memory stored as compute scales poorly due to the matrix multiply for the size of your hidden state vector. If in a couple months we have a new differentiable memory architecture (a la neural Turing machine) all the work you did building a chip is outdated!
Starting with first principles of what you can efficiently do with current process technology combined with an understanding of computational neuroscience is what Kwabenas lab excels at.
It's actually very difficult to simulate the mixed analog digital asynchronous chips coming out of Kwabenas lab or elsewhere in the industry.
There are plenty of other academic chips that fail after tapeout. Kwabenas lab has a proven track record of taping out chips that does what he claims. So from a hardware perspective I'd rather bet on a guy who has successfully taped out dozens of chips in his lab, and have the rest stick to simulation.