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I asked an Intel chip designer about this and his opinion was that asynchronous processors are a "fantasy." His reasoning was that an asynchronous chip would still need to synchronize data communication within the chip. Apparently global clock synchronization accounts for about 20% of the power usage of a synchronous chip. In the asynchronous case, if you had to synchronize every communication, then the cost of communication is doubled.



Maybe. But the benefits could be really big. for example, for mcu's maxim was working on implementing it, and they talked about 85% energy savings.

http://electronics360.globalspec.com/article/4615/maxim-prep...


What do you mean by "synchronizing data communication within the chip"? For example, is there something that can be "synchronized" in a ring oscillator, the simplest kind of unclocked logic?


I think this has been garbled, but he's referring to synchronisation across clock and power domains.

Normal D flip-flops require that, at the time of the clock edge arriving, the inputs are not changing. If you violate this you get "metastability" and data loss. Special structures are needed when you move data from a fast-clocked area to a slower. On processors, usually the core is at one (maybe variable!) speed while the peripherals and DRAM are at a lower speed (what used to be called "front side bus").

As to the application for async, maybe he's right and maybe he isn't. There would have to be synchronisation to fixed external bus speeds, but 20% seems very high as a proportion of power consumption.




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