Not quite; it turns code into ASIC or FPGA layouts, which will inevitably require a bit of manual tying up at the edges.
"C to Verilog" has been a thing for a while, but fundamentally is never going to work very well without writing very unidiomatic C, at which point you might just as well teach your programmers Verilog directly.
Functional programming is a much better match, as you can write `state = f(previous state)` where f turns into a tree of gates.
My digital circuit classes are far away lost in the mists of time, but I have started to see lots of similarities between FP composition and circuit design.
Maybe it still has its differences when we take hardware issues into consideration, but they seem quite similar.
I'm still hoping for the Cambrian explosion in HDLs we need to see if the technology is to become accessible. Verilog/VHDL are in many ways stuck in the ALGOL era.
I wish yCombinator or equivalent would fund a company or organization that is dedicated to making a complete end-to-end opensource fpga ecosystem. The proprietary tools are crap.
"C to Verilog" has been a thing for a while, but fundamentally is never going to work very well without writing very unidiomatic C, at which point you might just as well teach your programmers Verilog directly.
Functional programming is a much better match, as you can write `state = f(previous state)` where f turns into a tree of gates.