It should be pointed out, for the edification of those who are not VLSI people, that transistors with an f_t of 100GHz are not the same thing as transistors from which one can build a credible 100GHz processor. f_t is the input frequency at which the gain through the transistor (biased in the linear region) is unity (1). This has some relation to how fast the transistor can switch from 0 to 1 when biased in the saturation region (the way digital logic works), but it is not 1:1. Likewise, the cycle time of a processor is the delay of the longest path from one flip-flop or latch (storage element) to another flip-flop that is expected to take 1 clock cycle. The length of this path is typically expressed as a multiple of the propagation delay of an inverter driving 4 other inverters (delay grows with output load, or fanout) (FO4 delays http://en.wikipedia.org/wiki/FO4). Typically, high-performance processor microarchitectures are designed with a 5 (Pentium IV) - 25 (slower but more power-efficient) FO4 delay critical path. Once you account for clock skew, jitter, process/temperature variation, etc., your processor frequency is 1 to 2 orders of magnitude lower than your transistors' f_t.
The authors of this paper are careful to point out that their graphene transistors' f_t is higher than CMOS transistors of the same gate length (240nm), but that is comparing with a ~12-year-old CMOS processes. Modern CMOS processes are faster than this (for instance, this paper http://wwwtw.vub.ac.be/elec/Papers%20on%20web/Papers/DLinten... assumes a 90nm RF CMOS process with an NMOS f_t of 150GHz). Graphene can certainly catch up once they figure out how to shrink the devices, but it will take more than productizing the current state-of-the-art to compete with CMOS.
1) These graphene transistors are faster than CMOS transistors of the same size, but CMOS transistors of the same size haven't been used for most purposes in about a decade. Modern CMOS transistors (the kind used in your Core 2 Duo or Core i7) are roughly twice as fast.
When this comes to market, the Von Neumann bottleneck compensation techniques will become obsolete in a way. However I would love to see how this will speed up computing in throughput, because this clearly is a major achievement.
I predict that no fewer than 16 meta-languages and API layers will be piled on top of existing development methodologies, and that all future operating system graphics will be rendered in fully textured 3D, and that development will consist of drag-and-drop objects.
So, in short, the end-user experience won't change at all.
(Sorry, I'm a little cranky at the moment. Too many slow applications for no bloody good reason.)
The bandwidth and latency differences between on-chip memory and off-chip memory are multiple orders of magnitude. Graphene improvement over silicon is only about 1 order of magnitude, so it will not eliminate the von Neumann bottleneck alone.
So, about 10 years until they make their way into pcs. Hopefully hard drives will be fast enough to keep up with these new processors by then. It'd be really frustrating to have a computer with a processor that's 50x as fast, but the computer only runs about 1.5x overall.
I don't think we will have "hard drives" then. The solid state disks are starting to come down in price and the speed is nice in comparison. But, yes, I feel your pain.
<3mm cores might be a great idea - as multicore programming evolves, this may make possible thousands or millions of cores running at very high clock speeds.
I don't think massive multicore is a good idea for many applications
But hey now, that's the problem of the applications, isn't it? There's probably quite a bit of exciting potential with what you can do with massive multicore architecture - slide 6 of the presentation you linked to being a very convincing reason why.
The authors of this paper are careful to point out that their graphene transistors' f_t is higher than CMOS transistors of the same gate length (240nm), but that is comparing with a ~12-year-old CMOS processes. Modern CMOS processes are faster than this (for instance, this paper http://wwwtw.vub.ac.be/elec/Papers%20on%20web/Papers/DLinten... assumes a 90nm RF CMOS process with an NMOS f_t of 150GHz). Graphene can certainly catch up once they figure out how to shrink the devices, but it will take more than productizing the current state-of-the-art to compete with CMOS.