Last time I complained here about the verification infrastructure of this project, someone gave that link.
I didn't like much of what I could find there.
What exactly are you trying to do?
In addition it would be good to have a set of assertions to maintain the sanity (read functional correctness) while experimenting with the design.
How are these implementations verified right now ? All I see are few assertions in chisel and small set of tests.
Comparing a real CPU against an ISA simulator is VERY HARD. There's counter instructions, there's interrupts, timers will differ, multi-core will exhibit different (correct) answers, Rocket has out-of-order write-back+early commit, floating point registers are 65-bit recoded values, some (required) ambiguity in the spec that can't be reconciled easily (e.g., storing single-precision FP values using FSD puts undefined values in memory, the only requirement being that the value is properly restored by a corresponding FLD).
We also use a torture tester that we'll open source Soon (tm).
Not sure. I'd look out for videos to show up at the RISC-V workshop that's ongoing (http://riscv.org/workshop-jan2016.html).
The problem is verification is where the $$$ is, so even amongst people sharing their CPU source code, they're less willing to share the true value-provided of their efforts. A debug spec is being developed and will be added to Rocket-chip to make this problem easier.
With that said, MIT gave a good talk at the RISC-V workshop about their works on verification, and we open sourced our torture tester at (http://riscv.org/workshop-jan2016.html).
The tests are not extensive. Just hand written assembly code testing one thing at a time AFAIK. As someone who used to lead ASIC verification projects for a living, I expected a lot more at a minimum.
I don't know what the Chisel stuff checks. Chisel doesn't do anything at the simulation stage I believe.
I guess if you are just playing around with CPU designs, you can use this stuff.
I would never sign off on going to tape out with just this stuff though. Apparently they've taped out over 11 times though!
You want to run the RTL and compare against the ISA simulator? I think you're on your own...