I'm the founder of a startup taping out of first test chip in May... Getting 100 chips back on a shuttle run (Also known as a multi project wafer, where mask costs are shared by multiple companies) will cost us around $250,000. That is just the cost of these first 100 chips. Mask costs for a modern (eg 28nm) process start at about $2 Million, and go up from there pretty quickly, but is based on a lot of factors. Once the masks are made though, it is roughly $5K a wafer (where you can have 100s of dies on a wafer.
This sounds really interesting. I don't know what too much of this means though. Can you recommend books or in depth articles about the process of ic making?
The Wikipedia articles on semiconductor manufacturing are pretty good. Far as ASIC's, I struggled a while to find a great resource on all aspects of design, verification, and prototyping. Here's the best one I found for you:
On top of that, there's the cost of the photomasks that print the samples for testing (and later production). They range from tens of thousands on oldest nodes to millions on newer ones. Every time you screw up and change the design you buy another mask. Hence, avoidance of new nodes by low volume groups, design/verification tools that can cost $1mil/yr a person, and heavy re-use of components.
One trick that's popular is called multi-project wafers: a mask and chip run that's shared by several people with high cost split among them. This is available through groups like MOSIS and X-Fab. Lets you test your design in [more] affordable pieces. Plus, tooling and overall cost has come down for older nodes which are still highly usable for many scenarios:
So, overall barrier to entry for ASIC design is expensive expertise, high-cost of proprietary tools, and cost of masks (or MPW's). Going cheap on all these still gives several hundred thousand for a useful design on a good node. Simpler, single-purpose chips on oldest nodes can be less than that, though. Here's an example:
We're aiming to begin disclosing architecture and software details in March, with talks at 3 or 4 major industry conferences between then and August. As I said, we have our 28nm shuttle run booked for May, so baring any major issues, we're aiming for a August/September public demonstration of our first chips.
We have already been evaluating architectural models and FPGA demonstrations with partners for the past couple of months, but we feel its better to wait for real silicon to publicly show benchmarks, but so far so good.
Makes sense. I look forward to that. Curious, could you post what a 28nm run cost you for what percentage? Might be enlightening to people wondering about the real-world cost of such things outside of confusing $/mm2, etc on many sites.
We're all taking 2 weeks off after tapeout, so depending on how much I'll want to work during those 2 weeks, I'm thinking about writing a very long (or series of) blog posts going over the entire process (From moving out to the bay area, going a bit crazy and deciding I wanted to get into semiconductors, to now taping out a chip). The thing I would have loved the most while working on this the past 2 and a half years would have been some first hand account that would have saved me a lot of time at the beginning. Plus you are totally right that there is not much information out there that breaks it down to the rest of tech industry folk.
That's awesome. See, it's stuff like this that's why you're among my favorite chip designers despite being new to the game. ;) Look forward to the write-up.
