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How old is this video? What is described would have barely been state of the art in the late 90s. 5 stage pipeline written in VHDL. This is now on every student's resume, as a project for their computer architecture class.

Their proposed "two-process" coding methodology for VHDL is weird. They pretend their entire CPU core is written in a total of 3 VHDL processes.

I guess their only argument is that their target a 180nm process (from 1991), which costs only $25K.




They intentionally chose an old design because they know all the patents have expired. Thus, they don't have to worry about licensing woes or anything like that. There are a number of situations where you don't need a fast processor, just a processor that is fast enough. Additionally, an older core means it's a smaller core, so they can stick more of them on an FPGA if they need to respond to several realtime events at once.


And not just for ISA, there's tons of patents on everything from the microarchitecture optimizations to ways of synthesizing things. "Up-to-date" textbooks that today's academics are using probably include plenty of infringing material because a good part of why they learn that is to eventually work for patent-holding firms to improve their I.P..

On the flip side, trade secrets obscure many great tricks in this industry, esp for analog, to try to reduce number of patent suits they get hit with if they expose their constructions. Plus for competitive advantage with consideration for cloners that ignore patent rules. So, one says we can't use many, good techniques where another says we can't know it.

The "joys" of OSS hardware...


I consider it completely sufficient if there is any true OSS hardware which is able to run Linux with acceptable performance. Of course big applications like LibreOffice won't make fun on such systems. However we have TeX etc. which runs well even on small systems. I remember writing my own TeX documents on an 8 MHz Atari ST, and it worked well!

I agree with the previous poster: "you don't need a fast processor, just a processor that is fast enough."

If some day we had a small OSS cpu for Linux with acceptable performance which could be implemented in pure SMD like the monster 6502 - that would be nice!


I always repost the same ones:

http://www.gaisler.com/index.php/products/processors/leon3

http://www.oracle.com/technetwork/systems/opensparc/index.ht...

Gaisler would be easier one to implement in ASIC. The Leon4 is a 4-core variant. In any case, the Leon3 and key I.P. are GPL'd specifically for open-source to build on it. SPARC ISA only require $99 fee to use SPARC-compatible line. OSS people just keep ignoring it. Meanwhile, academics have built on it and the Leon3FT variant is often used in space applications.

So, get either booting on a FPGA, install Linux, and have at it. :)



RISC-V is the best open one to get on right now. The ISA is well-designed plus open. There are simulators, high-speed CPU's, compilers, and so on for it. Surprisingly, many big companies are also backing it on top of the academics doing it. There's at least a dozen RISC-V implementations in progress.

Many examples here:

http://www.lowrisc.org/blog/2016/01/third-risc-v-workshop-da...

Arduino-style implementation:

https://github.com/pulp-platform/pulpino

Note: OpenRISC is not RISC-V. It was a competing ISA that's fallen to the wayside as RISC-V's popularity soared. It did get used in Milkymist IIRC. Best to ignore it except maybe out of personal curiosity in favor of RISC-V and SPARC.


Also very interesting: http://hwacha.org


The main problem with software is web browser these days. You can find niche browser engines that would be somewhat lightweight, but 80% of sites would not work correct with them.


Date on video shows April 4 2016. "Every student's resume" and yet I wager none have released their design in order to foster an open computing community.

The video clearly indicates their motivation to make silicon that won't get a C&D as soon as they get to market.


> This is now on every student's resume, as a project for their computer architecture class.

AFAICS the point is not to create the bestest fastest microarchitecture ever; I'm sure nobody, including the guys behind this jcore project, harbors any illusions of competing with high-performance cores from the likes of Intel or IBM on a shoestring budget.

But rather, the point was to pick a decent ISA (for instance, SuperH is apparently the basis for ARM Thumb, so code density is quite good) with a (hopefully!) patent-free implementation. And with an ecosystem so you can actually use it. I'm pretty sure "every student's comp arch class project" doesn't include upstreamed support in the Linux kernel, GCC, binutils, GDB, strace etc.




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